For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device, e.g. optimizing drive current for each device, becomes increasingly significant due to power management concerns.
Nonvolatile charge trap memory devices are typically fabricated on silicon wafers having a <100> crystal plane orientation orthogonal to the surface of the wafer. FIGS. 1A-B illustrate a top-down view and a magnified cross-sectional view, respectively, of a conventional nonvolatile charge trap memory device.
Referring to FIG. 1A, a silicon wafer 100 has a <100> crystal plane orientation orthogonal to the surface of the wafer (i.e. <100> orientation in the z-direction). A notch 102 is cut into silicon wafer 100 to provide an alignment mark during semiconductor processing. Conventional silicon wafers, such as silicon wafer 100, incorporate a notch oriented with the <110> crystal plane. That is, notch 102 is oriented to provide <110> orientation in both the x- and the y-directions. Semiconductor devices are typically fabricated along either the x- or the y-direction and thus have channel regions having channel lengths with <110> crystal plane orientation. For example, referring again to FIG. 1A, an active region 104 is formed in silicon wafer 100 and is oriented along the x-direction. A gate stack 106 is oriented along the y-direction and overlaps active region 104, forming a semiconductor device.
FIG. 1B is a magnified cross-sectional view of the semiconductor device of FIG. 1A taken along the a-a′ axis, i.e. the <100> z-direction is now shown in the plane of the paper. Referring to FIG. 1B, source and drain regions 108 are formed in active region 104 on either side of gate stack 106. A channel region 112 is thus defined in active region 104, in between source and drain regions 108 and underneath gate stack 106. Channel region 112, which has a channel length along the x-direction between source and drain regions 108, has <110> crystal plane orientation along the channel length as a result of the orientation of gate stack 106 with active region 104. However, a <110> crystal plane orientation for channel region 112 may not be optimal for a semiconductor device that incorporates channel region 112.